1. Field of the Invention
The present invention is generally in the field of electrical circuits. More particularly, the present invention relates to phase locked loop circuits.
2. Background Art
Phase locked loops (PLLs) can be used in electronic circuits to generate high frequency signals that are multiples of lower frequency reference signals. A PLL configured in this fashion can be part of a circuit for generating a local oscillation frequency for downconverting a received radio frequency (RF) signal to a baseband frequency. The RF signal can be combined with the PLL output in a mixer, where the mixer output signal will be a downconverted baseband signal. Typically, the desired RF signal to be downconverted will be adjacent to other RF signals with frequencies near the desired RF signal. If the PLL output has a large loop bandwidth, and thus a high phase noise, the adjacent RF signals near the desired RF signal will also be downconverted to the baseband frequency, thereby corrupting the desired signal. Thus, it is desirable for PLLs to exhibit low phase noise, when the received RF signals are in close proximity, for example in television applications.
According to conventional techniques for reducing the PLL loop bandwidth, and thus reducing the PLL output phase noise, a loop filter component of the PLL is designed with a large stabilizing capacitor. For a PLL implemented as an integrated circuit, the utilization of a large stabilizing capacitor imposes design difficulties. The large stabilizing capacitor may be designed into the integrated circuit, which uses significant die space, or the large stabilizing capacitor may be located off-chip, which imposes additional pin-out, component count, and an additional bill-of-materials item.
Thus, there is a need in the art for a solution to reduce PLL phase noise, while avoiding the disadvantages inherent in conventional solutions.